The present invention relates to a timing analysis method in logic LSI design and more specifically to a timing analysis method used to verify the operating speed of semiconductor integrated circuits.
In recent deep sub-micron generations of LSI semiconductor integrated circuits, the interconnection capacitance has been forming an increasingly important factor in determining the circuit operating speed. Interconnection capacitances are roughly classified into two groups: capacitances between signal nodes through which a signal current flows and power supply or ground and coupling capacitances between signal nodes. In recent years, the fine pattern process has increased the percentage of the node-to-node coupling capacitance relative to the node-to-power supply (ground) capacitance. These capacitances will be described below.
FIG. 1 is a circuit diagram illustrating device-to-device interconnection capacitances. A node N100 that interconnects inverters IV100 and IV102 and a node N102 that interconnects inverters IV104 and IV106 are formed in close proximity to each other. In this case, coupling capacitance Cc is present between the nodes N100 and N102. In addition, ground capacitance Cg exists between the node N100 and ground.
As the demand has increased for incorporating a system in its entirety into a single chip, the circuit scale of semiconductor integrated circuits has increased. For this reason, the technique of verifying the performance of chips that are increasing in circuit scale, especially their operating speed, has shifted from dynamic simulation requiring an enormous amount of verification time to static simulation allowing faster processing.
With conventional static timing analysis for semiconductor integrated circuits, it is impossible to compute the delay time associated with a certain node with coupling capacitance present between that node and another node in mind. This is due to the property of the static timing analysis that, at the time of analysis of a certain node, the potential at another node is unknown.
Thus, the static timing analysis is made heretofore in accordance with the following approaches.
A first approach is to neglect coupling capacitance. FIG. 2 is an equivalent circuit illustrating inter-device interconnection capacitance when the coupling capacitance is neglected. As shown in FIG. 2, a node N100 that interconnects inverters IV100 and IV102 and a node 102 that interconnects inverters IV104 and IV106 are formed in close proximity to each other. In this case as well, ground capacitance Cg is associated with the node N100 to be analyzed.
A second approach is to double the value of coupling capacitance Cc and add it to the ground capacitance. FIG. 3 shows an equivalent circuit in such a case. As shown in FIG. 3, a node N100 that interconnects inverters IV100 and IV102 together and a node 102 that connects inverters IV104 and IV106 together are formed in close proximity to each other. In this case, ground capacitance Cg and capacitance 2Cc twice the coupling capacitance Cc are associated with the node N100 to be analyzed.
A third approach is to convert the coupling capacitance Cc to ground capacitance with its value maintained. FIG. 4 shows an equivalent circuit in such a case. As shown in FIG. 4, a node N100 that interconnects inverters IV100 and IV102 and a node 102 that interconnects inverters IV104 and IV106 are formed in close proximity to each other. In this case, ground capacitance Cg and coupling capacitance Cc are associated with the node N100 to be analyzed.
However, the conventional approaches have the following problems.
In the first approach, the coupling capacitance is neglected. This supposes that, as shown in FIG. 5, the potential at node N102 varies (falls or rises) in the same direction as and simultaneously with the potential at the node N100 to be analyzed. Thus, the calculated delay time becomes less than the actual delay time except when the potentials at the two nodes vary simultaneously in the same direction.
In the second approach, the coupling capacitance Cc is doubled and then added to the ground capacitance Cg. This supposes that, as shown in FIG. 6, the potential at node N102 varies (falls or rises) in the opposite direction to and exactly simultaneously with the potential at the node N100 to be analyzed. Thus, except when the potentials at the two nodes vary simultaneously in opposite directions, the calculated delay time becomes more than the actual delay time.
In the third approach, the coupling capacitance Cc is added as it is to the ground capacitance Cg. This supposes that, as shown in FIG. 7, the potential at the node N102 is fixed. Thus, except when the potential at the node N102 is fixed, the calculated delay time becomes less than or more than the actual delay time.
That is, the conventional static timing analysis requires additional margin because the effect of the coupling capacitance cannot be reflected precisely. On the other hand, although conditions have been satisfied on static timing analysis, they may sometimes not be satisfied on actual chips.
It is therefore an object of the present invention to provide a fast and precise timing analysis method for semiconductor integrated circuits which permits the effect of coupling capacitance between interconnections to be reflected accurately.
According to a first aspect of the present invention, there is provided a timing analysis method for semiconductor integrated circuits comprising the steps of: determining maximum capacitance and minimum capacitance for each of nodes on a circuit; making static timing analysis, using the maximum capacitance and minimum capacitance, of paths comprising one or more of the nodes on the circuit to classify the paths into conformable paths that satisfy a predetermined constraint, nonconformable paths that do not satisfy the constraint, and undecided paths that belong to neither the conformable paths nor the nonconformable paths; and making dynamic timing analysis of the undecided paths.
With this timing analysis method, the maximum capacitance and minimum capacitance are determined for each node on a circuit. Static timing analysis is first made using the maximum capacitance and minimum capacitance to classify paths into conformable paths that satisfy a predetermined constraint, nonconformable paths that do not satisfy the constraint, and undecided paths that belong to neither the conformable paths nor the nonconformable paths. Dynamic timing analysis is then made of the undecided paths to allow them to fall into either conformable paths or nonconformable paths. The use of the dynamic timing analysis only for the paths that cannot be distinguished by the static timing analysis allows the time required for timing analysis to be reduced and precision analysis to be made.
According to a second aspect of the present invention, there is provided a timing analysis method for semiconductor integrated circuits comprising the steps of: determining maximum capacitance and minimum capacitance for each of nodes on a circuit; making static timing analysis of data nodes that carry data signals and clock nodes that carry clock signals with the maximum capacitance selected for the data nodes and the minimum capacitance selected for the clock nodes; classifying, on the basis of the result of the static timing analysis, paths comprising one or more of the nodes on the circuit into conformable paths that satisfy a setup constraint and undecided paths that do not belong to the conformable paths; and making dynamic timing analysis of the undecided paths.
With this timing analysis method, the maximum capacitance and minimum capacitance are determined for each node on a circuit. Static timing analysis is first made using the maximum capacitance and minimum capacitance to classify paths into conformable paths that satisfy a setup constraint and other paths that cannot be decided by the static timing analysis. Dynamic timing analysis is then made of the undecided paths to allow them to fall into either conformable paths or nonconformable paths. The use of the dynamic timing analysis only for the paths that cannot be distinguished by the static timing analysis allows the time required for timing analysis to be reduced and precision analysis to be made.
According to a third aspect of the present invention, there is provided a timing analysis method for semiconductor integrated circuits comprising the steps of: determining maximum capacitance and minimum capacitance for each of nodes on a circuit; making static timing analysis of data nodes that carry data signals and clock nodes that carry clock signals with the minimum capacitance selected for the data nodes and the maximum capacitance selected for the clock nodes; classifying, on the basis of the result of the static timing analysis, paths comprising one or more of the nodes on the circuit into conformable paths that satisfy a hold constraint and undecided paths that do not belong to the conformable paths; and making dynamic timing analysis of the undecided paths.
With this timing analysis method, the maximum capacitance and minimum capacitance are determined for each node on a circuit. Static timing analysis is first made using the maximum capacitance and minimum capacitance to classify paths into conformable paths that satisfy a hold constraint and other paths that cannot be decided by the static timing analysis. Dynamic timing analysis is then made of the undecided paths to allow them to fall into either conformable paths or nonconformable paths. The use of the dynamic timing analysis only for the paths that cannot be distinguished by the static timing analysis allows the time required for timing analysis to be reduced and precision analysis to be made.
According to a fourth aspect of the present invention, there is provided a timing analysis method for semiconductor integrated circuits comprising the steps of: determining maximum capacitance and minimum capacitance for each of nodes on a circuit; making first static timing analysis of data nodes that carry data signals and clock nodes that carry clock signals with the maximum capacitance selected for the data nodes and the minimum capacitance selected for the clock nodes; making second static timing analysis of the data nodes and the clock nodes with the minimum capacitance selected for the data nodes and the maximum capacitance selected for the clock nodes; classifying paths comprising one or more of the nodes on the circuit into conformable paths that, as the result of the first static timing analysis, satisfy a setup constraint, nonconformable paths that, as the result of the second static timing analysis, do not satisfy the setup constraint, and undecided paths that belong to neither the conformable paths nor the nonconformable paths; and making dynamic timing analysis of the undecided paths.
With this timing analysis method, the maximum capacitance and minimum capacitance are determined for each node on a circuit. Static timing analysis is first made using the maximum capacitance and minimum capacitance to classify paths into conformable paths that satisfy a setup constraint, nonconformable paths that do not satisfy the constraint, and undecided paths that belong to neither the conformable paths nor the nonconformable paths. Dynamic timing analysis is then made of the undecided paths to allow them to fall into either conformable paths or nonconformable paths. The use of the dynamic timing analysis only for the paths that cannot be distinguished by the static timing analysis allows the time required for timing analysis to be reduced and precision analysis to be made.
According to a fifth aspect of the present invention, there is provided a timing analysis method for semiconductor integrated circuits comprising the steps of: determining maximum capacitance and minimum capacitance for each of nodes on a circuit; making first static timing analysis of data nodes that carry data signals and clock nodes that carry clock signals with the maximum capacitance selected for the data nodes and the minimum capacitance selected for the clock nodes; making second static timing analysis of the data nodes and the clock nodes with the minimum capacitance selected for the data nodes and the maximum capacitance selected for the clock nodes; classifying paths comprising one or more of the nodes on the circuit into nonconformable paths that, as the result of the first static timing analysis, do not satisfy a hold constraint, conformable paths that, as the result of the second static timing analysis, satisfy the hold constraint, and undecided paths that belong to neither the nonconformable paths nor the conformable paths; and making dynamic timing analysis of the undecided paths.
With this timing analysis method, the maximum capacitance and minimum capacitance are determined for each node on a circuit. Static timing analysis is first made using the maximum capacitance and minimum capacitance to classify paths into conformable paths that satisfy a hold constraint, nonconformable paths that do not satisfy the constraint, and undecided paths that belong to neither the conformable paths nor the nonconformable paths. Dynamic timing analysis is then made of the undecided paths to allow them to fall into either conformable paths or nonconformable paths. The use of the dynamic timing analysis only for the paths that cannot be distinguished by the static timing analysis allows the time required for timing analysis to be reduced and precision analysis to be made.
According to a sixth aspect of the present invention, there is provided a timing analysis method for semiconductor integrated circuits comprising the steps of: determining coupling capacitance and ground capacitance for each of nodes on a circuit; determining the ratio of the coupling capacitance to the total capacitance of the coupling capacitance and the ground capacitance (coupling capacitance/total capacitance) for each of the nodes; classifying the nodes into a first group of nodes for which the ratio of the coupling capacitance is greater than a preset value and a second group of nodes for which the ratio of the coupling capacitance is not greater than the preset value; determining maximum capacitance and minimum capacitance for each of the nodes in the first group; determining maximum capacitance and minimum capacitance for each of the nodes in the second group; making first static timing analysis of data nodes that carry data signals and clock nodes that carry clock signals with the maximum capacitance that has been determined for either the first group or the second group of nodes selected for the data nodes and the minimum capacitance that has been determined for either the first group or the second group of nodes selected for the clock nodes; making second static timing analysis of the data nodes and the clock nodes with the minimum capacitance that has been determined for either the first group or the second group of nodes selected for the data nodes and the maximum capacitance that has been determined for either the first group or the second group of nodes selected for the clock nodes; classifying paths comprising one or more of the nodes on the circuit into conformable paths that, as the result of the first static timing analysis, satisfy a setup constraint, nonconformable paths that, as the result of the second static timing analysis, do not satisfy the setup constraint, and undecided paths that belong to neither the conformable paths nor the nonconformable paths; and making dynamic timing analysis of the undecided paths.
With this timing analysis method, the coupling capacitance and ground capacitance are determined for each node on a circuit. Static timing analysis is first made using the coupling capacitance and ground capacitance to classify paths into conformable paths that satisfy a setup constraint, nonconformable paths that do not satisfy the constraint, and undecided paths that belong to neither the conformable paths nor the nonconformable paths. Dynamic timing analysis is then made of the undecided paths to allow them to fall into either conformable paths or nonconformable paths. The use of the dynamic timing analysis only for the paths that cannot be distinguished by the static timing analysis allows the time required for timing analysis to be reduced and precision analysis to be made.
According to a seventh aspect of the present invention, there is provided a timing analysis method for semiconductor integrated circuits comprising the steps of: determining coupling capacitance and ground capacitance for each of nodes on a circuit; determining the ratio of the coupling capacitance to the total capacitance of the coupling capacitance and the ground capacitance for each of the nodes; classifying the nodes into a first group of nodes for which the ratio of the coupling capacitance is greater than a preset value and a second group of nodes for which the ratio of the coupling capacitance is not greater than the preset value; determining maximum capacitance and minimum capacitance for each of the nodes in the first group; determining maximum capacitance and minimum capacitance for each of the nodes in the second group; making first static timing analysis of data nodes that carry data signals and clock nodes that carry clock signals with the maximum capacitance that has been determined for either the first group or the second group of nodes selected for the data nodes and the minimum capacitance that has been determined for either the first group or the second group of nodes selected for the clock nodes; making second static timing analysis of the data nodes and the clock nodes with the minimum capacitance that has been determined for either the first group or the second group of nodes selected for the data nodes and the maximum capacitance that has been determined for either the first group or the second group of nodes selected for the clock nodes; classifying paths comprising one or more of the nodes on the circuit into nonconformable paths that, as the result of the first static timing analysis, do not satisfy a hold constraint, conformable paths that, as the result of the second static timing analysis, satisfy the hold constraint, and undecided paths that belong to neither the nonconformable paths nor the conformable paths; and making dynamic timing analysis of the undecided paths.
With this timing analysis method, the coupling capacitance and ground capacitance are determined for each node on a circuit. Static timing analysis is first made using the coupling capacitance and ground capacitance to classify paths into conformable paths that satisfy a hold constraint, nonconformable paths that do not satisfy the constraint, and undecided paths that belong to neither the conformable paths nor the nonconformable paths. Dynamic timing analysis is then made of the undecided paths to allow them to fall into either conformable paths or nonconformable paths. The use of the dynamic timing analysis only for the paths that cannot be distinguished by the static timing analysis allows the time required for timing analysis to be reduced and precision analysis to be made.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.